This invention relates to differential input buffers, and more particularly to differential buffers that are relatively insensitive to input conditions.
Matching of delays in electronic circuits is a long-standing design challenge. One of many applications that require matched delays is a zero-delay buffer that uses a PLL to synchronize outputs to inputs. The PLL adjusts the circuit delay to exactly match the clock period and thus the apparent delay of the zero-delay buffer is zero with respect to the clock.
FIG. 1 shows a zero-delay buffer that requires precise delay matching. Zero-delay buffer chip 10 may be integrated with a larger system or may be sold as a stand-alone zero-delay chip. Clock source 18 generates a reference clock CLK that is input to chip 10. This reference clock passes through input buffer 22 and is compared in phase to a feedback clock FB that passes through a similar input buffer 24. Phase comparator 12 compares the phases of CLK and FB and activates charge pump 14 to charge or discharge filter capacitor 20. As capacitor 20 is charged or discharged, the voltage across capacitor 20 changes, and voltage-controlled oscillator VCO 16 senses the capacitor voltage and adjusts the output frequency of an output clock that is buffered by output buffer 26.
The FB clock output by buffer 26 can drive other logic directly, or additional internal or external buffering can generate other clocks. Many PLL""s can be included in parallel to separately drive and adjust parallel clock lines that are synchronized to each other and to the reference clock.
Input buffers 22, 24 must to have closely matched delays. Otherwise a phase error is introduced that can cause VCO 16 to output the wrong frequency. The physical design of input buffers 22, 24 can be closely matched to avoid skews. Unfortunately, the electrical characteristics of the signal traces and drivers of the reference clock and feedback clock can differ. For example, clock source 18 may have a different driver than output buffer 26, and may drive less current or may drive signal edges more slowly. The metal traces for CLK and FB may also differ. For example the FB clock trace may be much shorter than the reference clock CLK trace. Thus the input conditions of the signals input to input buffers 22, 24 can differ considerably. Input buffers that can adapt for such external mis-matches are desirable.
There are many measurable input conditions that can mismatch as a result of such differences in external drivers and traces. For example, measurements of rise and fall times or slew rates, high and low amplitudes and even root-mean-square (RMS) voltages of signals can differ. Often differential rather than single-ended signals are used. Then additional input-signal characteristics can be mis-matched, such as differential crossing or cross-over points and common-mode voltages.
One commonly-used circuit for input buffers is the differential amplifier. FIG. 2 shows a prior-art differential input buffer. Inputs signals V+, Vxe2x88x92 are applied to the gates of n-channel differential transistors 36, 38, respectively. Resistor loads 32, 34 supply matched currents to transistors 36, 38, and these currents are combined at current sink 30. Differential outputs VOxe2x88x92, VO+ are taken from the drains of transistors 36, 38, respectively.
Such a differential buffer is delay-independent of common-mode level within a certain range. The differential transistors tend to linearize I/Vin, for a range of about 2 xcex94V, where xcex94V is the gate bias of transistors 36, 38, or Vgsxe2x88x92Vt, where Vgs is the average gate-to-source voltage and Vt is the n-channel transistor threshold voltage. However, non-linear delays occur beyond this 2 xcex94V range.
One source of delay variation is the parasitic tail capacitance represented by tail capacitor 28. When inputs V+, Vxe2x88x92 differ by more than 2 xcex94V, one of differential transistors 36, 38 may turn off completely. All of the tail current then flows through the other differential transistor. As the input voltage V+ or Vxe2x88x92 rises even more, the tail voltage also rises rather than remaining constant. The rising tail voltage charges tail capacitor 28, requiring some of the current.
It is thus desirable to avoid operating at higher input voltages where such delay variations due to charging and discharging of the tail capacitance occur. It is desirable to avoid large differences in differential input voltages V+, Vxe2x88x92. It is desired to limit the difference between differential inputs V+, Vxe2x88x92. Adjusting for input conditions that exceed 2 xcex94V is desirable to produce better delay matching of differential input buffers.